Freescale Semiconductor /MKE15Z7 /TSI /SSC2

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Interpret as SSC2

MOVE_REPEAT_NUM=00000, MOVE_NOCHARGE_MIN=0000, MOVE_STEPS_NUM=000

Description

TSI SSC Register 2

Fields

MOVE_REPEAT_NUM	MOVE_REPEAT_NUM 0 (00000): The up_down counter will be updated for every sample-charge cycle. 1 (00001): The up_down counter will be updated for every 2 sample-charge cycles. 2 (00010): The up_down counter will be updated for every 3 sample-charge cycles. 3 (00011): The up_down counter will be updated for every 4 sample-charge cycles. 4 (00100): The up_down counter will be updated for every 5 sample-charge cycles. 5 (00101): The up_down counter will be updated for every 6 sample-charge cycles. 6 (00110): The up_down counter will be updated for every 7 sample-charge cycles.
MOVE_STEPS_NUM	MOVE_STEPS_NUM 0 (000): The added value for up-down counter is 0. 1 (001): The added value for up-down counter is 1. 2 (010): The added value for up-down counter is 2. 3 (011): The added value for up-down counter is 3. 4 (100): The added value for up-down counter is 4. 5 (101): The added value for up-down counter is 5. 6 (110): The added value for up-down counter is 6. 7 (111): The added value for up-down counter is 7.
MOVE_NOCHARGE_MAX	MOVE_NOCHARGE_MAX
MOVE_NOCHARGE_MIN	MOVE_NOCHARGE_MIN 0 (0000): The SSC output bit 1’s min period will be (1 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycle of system clock. 1 (0001): The SSC output bit 1’s min period will be (2 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. 2 (0010): The SSC output bit 1’s min period will be (3 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. 3 (0011): The SSC output bit 1’s min period will be (4 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. 4 (0100): The SSC output bit 1’s min period will be (5 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. 5 (0101): The SSC output bit 1’s min period will be (6 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. 6 (0110): The SSC output bit 1’s min period will be (7 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. 7 (0111): The SSC output bit 1’s min period will be (8 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. 8 (1000): The SSC output bit 1’s min period will be (9 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. 9 (1001): The SSC output bit 1’s min period will be (10 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. 10 (1010): The SSC output bit 1’s min period will be (11 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. 11 (1011): The SSC output bit 1’s min period will be (12 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. 12 (1100): The SSC output bit 1’s min period will be (13 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. 13 (1101): The SSC output bit 1’s min period will be (14 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. 14 (1110): The SSC output bit 1’s min period will be (15 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock. 15 (1111): The SSC output bit 1’s min period will be (16 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock.

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